// +FHDR----------------------------------------------------------
// Copyright (c) 2023, RJMicro Technology Co.,Ltd.
// RJMicro Confidential Proprietary
// ---------------------------------------------------------------
// FILE NAME       : .v
// DEPARTMENT      : IC Dept
// AUTHOR          :
// AUTHOR'S EMAIL  :
// ---------------------------------------------------------------
//
// Description     :
// 12'h000  CR1
// 12'h004  CR2
// 12'h008  SMCR
// 12'h00C  DIER
// 12'h010  SR
// 12'h014  EGR
// 12'h018  CCMR1
// 12'h01C  CCMR2
// 12'h020  CCER
// 12'h024  CNT
// 12'h028  PSC
// 12'h02C  ARR
// 12'h034  CCR1
// 12'h038  CCR2
// 12'h03C  CCR3
// 12'h040  CCR4
// 12'h048  DCR
// 12'h04C  DMAR
// 12'h030  RCR
// 12'h044  BDTR
// 12'h050  CMP01
// 12'h054  CMP23
// 12'h058  CMP45
// -FHDR
// ---------------------------------------------------------------

module epwm_regfile (
    input                  hclk                ,
    input                  hrstn               ,

    input                  hready              ,
    input  [31:0]          haddr               ,
    input                  hwrite              ,
    input  [01:0]          htrans              ,
    input  [02:0]          hsize               ,
    input  [31:0]          hwdataa              ,

//   output                 hreadyout           ,
//   output                 hreadyout_peri      ,
    input                   hsel_epwm           ,
    output [31:0]           hrdata_epwm
);

// ------------------------------------------------------------
// AHB write read enable
// ------------------------------------------------------------
wire            ahb_cs    = hsel_epwm & hready & htrans[1];
wire            read_en   = ahb_cs & (~hwrite);
reg     [11:2]  addr;
reg             write_en;
reg     [31:0]  ff_rdata;

always @(posedge hclk or negedge hrstn) begin
    if (~hrstn) begin
        addr      <= 6'h0;
        write_en  <= 1'h0;
    end else begin
        addr      <= haddr[11:2];
        write_en  <= ahb_cs & (~hwrite);
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        hrdata_epwm <= 32'b0;
    else if (read_en) 
        hrdata_epwm <= ff_rdata[31:0];
end

// ------------------------------------------------------------
// Internal Signals
// ------------------------------------------------------------


// ------------------------------------------------------------
// write_process
// ------------------------------------------------------------


// ------------------------------------------------------------
// read_process
// ------------------------------------------------------------


always @ (*) begin
    ff_rdata = 32'h0;
    if (read_en) begin
        case (addr[11:2])
            default: ff_rdata = 32'h0;
        endcase
    end
end
// ------------------------------------------------------------
// Assign
// ------------------------------------------------------------
// ------------------------------------------------------------
// End of the module
// ------------------------------------------------------------
endmodule
